1. Field of the Invention
The present invention relates to a semiconductor memory device and manufacturing method therefor, and more particularly, to a cell array region of a NOR-type mask ROM device and a fabricating method therefor.
2. Description of the Related Art
In semiconductor memory devices, mask ROM devices are characterized in that information programmed in a memory cell is not erasable, nor is new information storable in a specific cell. The mask ROMs have a relatively simple fabricating process, as compared with flash memory devices. They can be used for example in applications where a user desires a code to be stored, and can be manufactured within a relatively short time. A method of programming the mask ROMs is to selectively implant impurities into the channel region of a desired cell during their manufacture in such a way as to change the threshold voltage of the desired cell.
FIG. 1 is a plan view showing a portion of a cell array region in a conventional NOR-type mask ROM. Referring to FIG. 1, a plurality of sub-bit lines SBL1, SBL2, SBL3, SBL4, . . . , comprised of a buried N+ layer, are arranged parallel to one another on a semiconductor substrate. A plurality of word lines WL1, WL2, WL3, . . . which intersect the sub-bit lines SBL1, SBL2, SBL3, SBL4, . . . at right angles, are arranged parallel to each other. In addition, a plurality of bit lines BL1, BL2, . . . are formed parallel to the sub-bit lines SBL1, SBL2, SBL3, and SBL4. The bit lines BL1, BL2, . . . are connected to the sub-bit lines through a select transistor to transmit an external electrical signal. In particular, the sub-bit lines SBL1, SBL2, SBL3, SBL4, . . . operate as a source/drain of a memory cell transistor. The region between the sub-bit lines SBL1, SBL2, SBL3, SBL4, . . . disposed in the lower part of the word lines is used as a channel region. The word lines WL1, WL2, WL3, . . . are formed on the source/drain region and channel region to operate as gate electrodes.
FIGS. 2A, 3A and 4A are sectional views for explaining a method for fabricating a conventional NOR-type mask ROM cell taken along line A-Axe2x80x2 shown in FIG. 1, while FIGS. 2B, 3B and 4B are sectional views for explaining a method of fabricating the same taken along line B-Bxe2x80x2 shown in FIG. 1. Referring to FIGS. 2A and 2B, a P-well region 13 is formed over a semiconductor substrate 11. A sacrificial oxide layer 15, is provided over the surface of the P-well region 1, and on top of the sacrificial oxide layer 15 a first photoresist pattern 17 is formed using a photo mask in which the sub-bit lines of FIG. 1 are drawn. Then, N-type impurities 19 such as arsenic (As) are implanted on the surface of the P-well region 13 using the first photoresist pattern 17 as an ion implantation mask, to form a plurality of N-type impurity regions 21 parallel to one another.
Referring to 3A and 3B, the first photoresist pattern 17 and the sacrificial oxide layer 15 are removed to expose the plurality of N-type impurity regions 21 formed on or on the surface of the P-well region 13. Then, a gate oxide layer 23 such as a thermal oxide layer is formed on the surface of the resulting material. Consequently, impurities within the N-type impurity regions 21 are activated to form a plurality of buried N+ layers SBL1, SBL2, SBL3, and SBL4, which are parallel to one another. In this case, impurities within the N-type impurity regions 21 are diffused along the boundary between the gate oxide layer 23 and the P-well region 13 to form tails (TL) on the edges of each of the buried N+ layers SBL1, SBL2, SBL3, and SBL4. This is because, when the gate oxide layer, i.e. thermal oxide layer, is formed with the N-type impurity regions 21 exposed, the speed at which impurities within the N-type impurity regions 21 are diffused into the bulk region of the P-well region 13 is faster than the speed at which the same impurities are diffused along the surface of the P-well region 13. This phenomenon is referred to as the xe2x80x9coxidation enhanced diffusionxe2x80x9d effect. This makes the gap between the plurality of buried N+ layers SBL1, SBL2, SBL3, and SBL4 narrower than the original gap between the N-type impurity regions 21. As a result, some problems occur in that the width of an isolation area as well as the effective channel length of cell transistors is reduced since the gap between buried N+ layers SBL1, SBL2, SBL3, and SBL4 operating as a source/drain region is narrower.
Furthermore, the plurality of buried N+ layers SBL1, SBL2, SBL3, and SBL4 serve as common source and drain lines of cell transistors. Thus, it is preferable that the plurality of buried N+ layers SBL1, SBL2, SBL3, and SBL4 are doped to as high a concentration as possible, in order to reduce their resistance. However, as the concentration of impurities in the plurality of buried N+ layers SBL1, SBL2, SBL3, and SBL4 becomes higher, the tails (TL) become longer and the effective channel of cell transistors becomes shorter.
Additionally, at the initial stage of a thermal oxidation process for forming the gate oxide layer 23, an out-diffusion of impurities, i.e., arsenic ions, within the N-type impurity regions 21 occurs. This causes the out-diffused N-type impurities to be moved again on the surfaces of the P-well region 13 and a substrate of the peripheral circuit region (not shown), which may locally change the concentration of impurities on the substrate surfaces. If the impurity concentration on the substrate surfaces turns out to be uneven, an electrical characteristic such as the threshold voltage of an MOS transistor will also be uneven, so that malfunction of the circuit occurs.
A first conductive layer (not shown) such as a doped polysilicon layer is provided on top of the gate oxide layer 23. The first conductive layer is patterned to form a plurality of word lines (WL2) 25 which intersect the plurality of buried N+ layers SBL1, SBL2, SBL3, and SBL4 at right angles. Next, on the substrate over which the plurality of word lines 25 is formed, a second photoresist pattern 26, which opens the desired cell using a program mask shown in FIG. 1, is formed. Then, P-type impurities 27 such as boron (B) ions are implanted selectively on the channel region of the desired cell, using the second photoresist pattern 26 as an ion implantation mask. The channel concentration of the desired cell is higher than the original channel concentration, so that the threshold voltage of the desired cell is increased. As a result, the desired cell is programmed.
Referring to FIGS. 4A and 4B, the second photoresist pattern 26 is removed. A interlayer insulating layer 28 is provided over the entire surface of the semiconductor substrate 11 from which the second photoresist pattern 26 has been removed. Then, bit line contact holes (not shown) which expose a predetermined region among the buried N+ layers SBL1, SBL2, SBL3, and SBL4 are formed, patterning the interlayer insulating layer 28. A second conductive layer (not shown), e.g., a metal layer is provided over the entire of the semiconductor substrate 11 on which the bit line contact holes have been formed. A plurality of bit lines BL1 and BL2 which intersect the plurality of word lines 25 at right angles are formed by patterning the second conductive layer. First and second bit lines BL1 and BL2 are each electrically connected to the N+ layers SBL1, SBL2, SBL3, and SBL4 through the bit line contact holes.
As described above, according to the conventional art, tails (TL) occur when a plurality of buried N+ layers SBL1, SBL2, SBL3, and SBL4 are formed on the surface of a semiconductor substrate. As a result, the gap between the buried N+ layers SBL1, SBL2, SBL3, and SBL4 becomes narrower by a subsequent thermal process, in which case impurities outwardly diffused from the plurality of buried N+ layers SBL1, SBL2, SBL3, and SBL4 are implanted again into the surfaces of the semiconductor substrate 11 in a P-well region within a cell area, and a peripheral circuit region. This not only reduces the punchthrough margin of a cell transistor, but also degrades the isolation properties of the cell transistor to make reducing the area of a cell array region difficult. Thus, the conventional art is not suitable for embodying densely integrated mask ROMs. Further, the surface concentration of channel regions of MOS transistors formed on a peripheral circuit region, as well as that of channel regions of cell transistors which are not programmed, is not uniform, which may cause a malfunction in the mask ROMs.
To address the above limitations, it is an object of the present invention to provide a cell array region of a NOR-type mask ROM device, which not only increases the punchthrough margin of a cell transistor but also improves the isolation characteristic between cell transistors.
It is another object of the present invention to provide a method for fabricating a cell array region of a NOR-type mask ROM device which is capable of containing cell transistors and peripheral circuit transistors of equal characteristics, as well as improving a punchthrough margin and isolation properties between cell transistors.
To achieve the object of the invention, there is provided a cell array region of a NOR-type mask ROM device including a plurality of word lines which are formed on a semiconductor substrate parallel to one another, a plurality of sub-bit lines which intersect the top portion of the plurality of word lines at right angles, a plurality of trench regions formed on the semiconductor substrate, the plurality of trench regions exposing the semiconductor substrate between the plurality of sub-bit lines and the plurality of word lines, and a plurality of bit lines electrically connected with the sub-bit lines.
In this case, the semiconductor substrate is either a semiconductor substrate in which a P-well region is formed, or a P-type semiconductor substrate. Further, the semiconductor substrate is preferably a silicon substrate.
A gate insulating layer interposes between the plurality of word lines and the semiconductor substrate, and a capping layer pattern is stacked on each word line. Each word line and the capping layer pattern stacked thereon form a word line pattern. A spacer made of an insulating layer is formed along the sidewall of each word line pattern. Thus, each word line is insulated by the spacer and the capping layer pattern. Each sub-bit line passes the top of the plurality of word line patterns and contacts the semiconductor substrate between the plurality of word lines. Source or drain regions of cell transistors are formed on the surface of the semiconductor substrate contacting each sub-bit line. The source and drain regions are doped with impurities of the opposite conductive type to the semiconductor substrate, such as N-type impurities.
A capping layer pattern is stacked on each source line as well as each sub-bit line. Each sub-bit line and the capping layer pattern stacked thereon form a sub-bit line pattern. It is preferable to further include field channel stop layers, doped with the same type of conductive impurities as the semiconductor substrate, on the sidewalls and the bottom of the trench regions. The semiconductor substrate surface intersecting the plurality of word lines among the semiconductor substrate surfaces between the sub-bit lines, corresponds to a channel region of each cell transistor. A channel region of at least one programmed cell transistor among a plurality of cell transistors has a higher impurity concentration than the semiconductor substrate does. The bit lines pass the top of sub-bit lines and are arranged parallel thereto.
To achieve another object of the present invention, there is provided a method of fabricating a cell array region of a NOR-type mask ROM device, including the steps of forming a plurality of word line patterns which are parallel to one another on a semiconductor substrate, forming a plurality of sub-bit line patterns which intersect the plurality of word line patterns at right angles after exposing the semiconductor substrate between the plurality of word line patterns, etching the semiconductor substrate exposed by the plurality of word line patterns and the plurality of sub-bit line patterns to form a plurality of trench regions, forming an interlayer insulating layer on the entire surface of the semiconductor substrate on which the plurality of trench regions have been formed, patterning the interlayer insulating layer to form a bit line contact hole exposing an active region which is connected with a sub bit line forming sub-bit line pattern, and forming bit lines which are parallel to each sub-bit line pattern and are electrically connected with each sub-bit line through each bit line contact hole.
Forming the plurality of word line patterns includes the steps of forming a gate insulating layer on the semiconductor substrate, sequentially forming a conductive layer and a capping layer on the gate insulating layer, and sequentially patterning the capping layer and the conductive layer. The conductive layer is comprised of a doped polysilicon layer or metal polycide layer. Thus, each word line pattern is formed of a word line made of a conductive layer pattern, and a capping layer pattern stacked thereon.
Forming the plurality of sub-bit line patterns includes the steps of forming a spacer made of an insulating layer such as a high temperature oxide (HTO) layer along the sidewall of the plurality of word line patterns, removing a gate insulating layer remaining on the semiconductor substrate between the word line patterns to expose the semiconductor substrate between the plurality of the word line patterns, sequentially forming a conductive layer and a capping layer over the entire surface of the resulting material, and sequentially patterning the capping layer and the conductive layer to form a plurality of sub-bit lines crossing the plurality of word line patterns. Each sub-bit line pattern is formed of a sub-bit line made of a conductive layer pattern and a capping layer pattern stacked thereon. The conductive layer may be comprised of a polysilicon layer doped with the opposite type of conductive impurities to the semiconductor substrate, or a metal polycide layer. Further, the capping layer may be formed of the same material layer as that used in forming the plurality of word line patterns. Prior to forming the spacer, the step of forming impurity regions doped with the opposite type of conductive impurities to the semiconductor substrate, on the surface of semiconductor substrate between the word line patterns may be further included. Impurities within the conductive layer forming the sub-bit lines may form impurity regions by auto doping during a manufacturing process. The impurity regions are doped at a high concentration of more than 1018/cm3.
The plurality of trench regions are formed by etching the semiconductor substrate using capping layer patterns forming the plurality of word line patterns, a spacer formed along the sidewall of the plurality of word line patterns, and capping layer patterns forming the plurality of the sub-bit line patterns as a self-aligned etching mask. The plurality of trench regions are formed deeper than the impurity regions. Preferably, the same type of conductive impurities as the semiconductor substrate are implanted over the surface of the semiconductor substrate on which the plurality of trench regions have been formed, to form field channel stop layers on the sidewalls and the bottom of the plurality of trench regions.
As described in the foregoing, the present invention, forming sub-bit lines subsequently after forming a plurality of word lines, can significantly reduce the time for a thermal process which is conducted on source and drain regions of a cell transistor, as compared with the conventional art. Such reduction results in improvement of the punchthrough margin of cell transistors, thereby providing an enhanced embodiment of a highly integrated mask ROM device. Furthermore, an isolation characteristic can be improved by forming trench regions between source and drain regions.